The recent rapid growth in demand for wireless communications services has been a strong motivation for designing more highly integrated RF ICs with low operating voltage, low power, and low cost, while meeting performance requirements for wireless systems. Scaled CMOS technologies can be more effectively utilized to improve the integration level of the RF transceivers and synthesizers, while resulting in further improvements in power dissipation and cost.
A frequency synthesizer, used to generate a local oscillator frequency, is one of the major building blocks for wireless communications devices. Since the synthesizer influences the performance of the overall wireless systems, it should have high performance, specifically low phase noise and low spurious tones or signals (hereinafter, referred as spurs). Modern wireless communications systems require frequency synthesizers to cover the frequency range from about 800 MHZ to 2.5 GHz.
A PLL-based synthesis technique offers high integration level, low power dissipation, small chip area, high reliability, and predictable performance. The comparison frequency in an integer-N PLL frequency synthesizer is equal to the channel frequency spacing. Thus, the integer-N frequency synthesizer with A small channel frequency spacing is not suitable for a system required fast frequency acquisition time because the loop bandwidth should be narrow enough to keep the system stable. Another drawback comes from the inverse relationship between the frequency spacing and in-band phase noise. As the frequency spacing decreases, the divide ratio of the programmable frequency divider for a given local oscillator frequency range must increase. The higher the divide ratio, the worse the phase noise inside the loop bandwidth close to the carrier frequency. The in-band phase noise is higher than the system noise floor by about an amount of 20logN, where N is the total divide ratio. The output spurs are also related to the loop bandwidth. Thus, trade-offs are needed in determining the loop bandwidth and loop performance.
A fractional-N frequency synthesis technique enables the use of reference frequencies larger than the channel frequency spacing (U. L. Rhode, Digital PLL Frequency Synthesizers: Theory and Design, Prentice-Hall, Englewood Cliffs, N.J., 1983.). This technique is able to considerably reduce the divide ratio N in the loop for the same frequency spacing as that in an integer-N synthesizer, while using the highest possible reference frequency. This technique has a significant beneficial effect on the in-band phase noise performance of the synthesized output. The possibility of using a higher reference frequency also opens up the way to a wider loop bandwidth, hence faster switching time. Using a reference frequency higher than the channel frequency spacing can reduce the reference spurs at the output. However, use of the fractional-N technique introduces periodic disturbances in the loop, resulting in large fractional spurs at all multiples of the offset frequency depending on the fractional data.
A noise shaping technique using a high-order sigma-delta modulator is used to suppress the fractional spurs. One example of the technique can be found in A Multiple Modulator Fractional Divider, by B. Miller and R. J. Conley (IEEE Transactions on Instrumentation and Measurement, vol. 40, pp. 578-583, June 1991.). The idea is to eliminate the low frequency phase error by rapidly switching the divide ratio between different ratios to eliminate the gradual phase error at the phase-frequency detector. By changing the divide ratio rapidly between different values, the phase error occurs in both polarities, positive as well as negative, and in an accelerated rate that explains the phenomena of high frequency noise push-up.